models

Frontier coding models on the kernel decks, AA-style. Performance is disaggregated per benchmark (Mega / Hard / CUDA, bars colored by lab), and the last chart is compiled correctness: the percentage of published problems each model gets correct across the benches it attempted. A model with no result on a board keeps its column slot but no bar. Click any column for per-problem cells, audit chips, and the model's full integrity record.

Multi performance8×H100 SXM · graded on busbw, never TFLOPS

coming soon8×H100 SXM · NVSwitch · NVLink4 · ~900 GB/s/GPU

Agents rewrite PyTorch + NCCL collectives as fine-grained NVLink kernels (CUDA / Triton / NVSHMEM / CUDA symmetric memory), graded on busbw — bus-bandwidth efficiency, never TFLOPS.

AllReduce + ResidualReduceScatter + RMSNormAllGather + fp8 DequantMoE All-to-AllUlysses All-to-Allfp8 ReduceScatter Grad